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Design Considerations Towards Optimal High-Resolution Wide-Bandwidth Time-Interleaved ADCs

IEEE SSCS Santa Clara Valley Section Technical Talk Wednesday January 26, 2022, 6:00-7:00PM Speaker: Dr. Athanasios Ramkaj Abstract: The ever-growing demand for higher throughput and bandwidth in next-generation communication and instrumentation systems, has spurred the need for multi-GHz sample rate/bandwidth ADCs with high spectral purity (10b+) and good power efficiency. A very popular way to boost the sample rate beyond the capabilities of a standalone converter is parallelism of identical sub-ADCs in a time-interleaved (TI) fashion. However, TI-ADCs come with interleaving (IL) errors due to offset, gain, timing, and bandwidth mismatches between the sub-ADCs. Further, the input front-end loading, clock generation/distribution, and calibration to compensate for sub-ADC/IL errors impose extra design overheads. Hence, the sub-ADC as well as the IL factor and interleaver architecture are critical choices towards optimal performance. This talk first reviews time-interleaving as a popular way of extending the sample rate of a standalone converter, and focuses on key aspects such as IL errors and interleaver architectures. A model is introduced to compare the achievable bandwidth and sampling accuracy of different interleaver architectures over four deep-scaled CMOS process nodes. Finally, a design example of a 28nm CMOS 5GS/s 12-bit 8x-TI Hybrid ADC is presented, putting the discussed principles into practice. Bio: Athanasios Ramkaj received the M.Sc. degree (cum laude) in electrical engineering (microelectronics) from TU Delft, Delft, The Netherlands, and the Ph.D. degree (summa cum laude) in electrical engineering from KU Leuven, Leuven, Belgium, in 2014 and 2021, respectively. His Ph.D. research was in the field of multi-GHz bandwidth power-efficient Nyquist A/D converters. Since June 2021, he has been with the Murmann Mixed-Signal Group, Stanford University, Stanford, CA USA, as a postdoctoral research fellow, working on multi-GHz ultra-low jitter A/D solutions. From 2013 to 2014, he was a research intern in the Central Research & Development Department of NXP Semiconductors, Eindhoven, The Netherlands, where he worked on GHz-range A/D converters for communication systems. In 2019, he was a research/design intern with the High-Speed Data Converters group of Analog Devices Inc., Wilmington, MA USA, investigating highly integrated solutions for bandwidth extension of next generation RF A/D converters. His main research interests include high-speed/bandwidth high-resolution RF sampling A/D converters, high-speed analog/mixed-signal circuits for wireline/wireless systems, and ultra-wideband receiver front ends. Dr. Ramkaj is the recipient of the 2021 Analog Devices Outstanding Student Designer Award, the 2019-2020 IEEE Solid-State Circuits Society Predoctoral Achievement Award, and the 2015 IEEE PRIME Golden Leaf Best Student Paper Award. He also serves as a reviewer for the IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS, and the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I & II.