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Branching & Best Stage Effort - Delay in Multistage Logic Network | Know - How

This video on "Know-How" series helps you to obtain a optimum delay for a multistage logic network with different stages and branches involved. Also, the dimensions of individual gates are calculated and best stage aspect (W/L) ratio for PMOS and NMOS of each logic gate is also shown. To understand the basic linear delay model for basic CMOS gates watch the video link shared below: (which shows the calculation of logical effort and parasitic delay)    • Effort Delay, Logical Effort, Electri...   To understand about the transistor sizing - setting (W/L) ratio of PMOS & NMOS:    • Transistor Sizing - Catalog of Skewed...   TimeCodes Delay in a Multistage Network: (0:00) Branching Effort & Path Effort: (00:48) Minimum delay of "N" stage path: (08:40) Best Stage Effort - Problem: (09:46) Best stage Effort - Path Delay Calculation: (10:58) Transistor Sizing - Logic Gate Dimensions: (16:38) Verfication of Path Delay: (22:00) Best Stage Effort - Estimation of (W/L) ratio:(24:32) Best Stage Effort - Final Multistage Logic Network: (28:29)