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Mixed-Signal Randomisation - Stimulus and Checkers

Mixed-Signal Randomisation - Stimulus and Checkers Constrained-random verification (CRV) is a well-established and successful methodology for digital designs and UVM has become the primary means to achieve this. The functional complexity in mixed-signal designs is increasing exponentially. Even a simple Power Management Unit can have hundreds or thousands of control bits and many modes of operation. To achieve good functional coverage, it is important to adopt a CRV approach for mixed-signal designs. This approach can help us manage a large verification space, including: checking analogue performance under a large set of programmable configurations; digital control system interaction with analogue circuits; covering unexpected corner cases in A/D interaction. To lower the bar for verification engineers to switch Device-Under-Test (DUT) abstractions between DMS and AMS a generic monitor will be presented. This monitor is agnostic to the DUT abstraction so the Verification engineer can work in the environment they are most comfortable in. This presentation shows some of the ways in which Renesas has applied UVM to mixed-signal designs and some of the benefits we gained by doing so. The work presented was the driving force in defining the UVM-MS standard.