Скачать с ютуб Presentation by NXP SEMICONDUCTORS - The road towards In-System Test for automotive ethernet в хорошем качестве

Presentation by NXP SEMICONDUCTORS - The road towards In-System Test for automotive ethernet

Recorded at the Siemens U2U Europe Summit 2023. Presenter: ARJEN BAKKER, Senior DFT Engineer, NXP Semiconductors Abstract: The SJA1110 successor SoC will be the first Automotive Zonal Ethernet Switch NXP device with Logic BIST inside to facilitate Functional Safety (ISO 26262). Using pseudo-random patterns, the logic can be self-tested within 2 milliseconds during power up of the device with a Stuck-At Test Coverage of 80%. The device made in 40nm technology (Global Foundries) contains a Switch IP supporting 8 PHY ports, an ARM Cortex-M7 microprocessor, RAM, ROM, OTP, security blocks and peripherals. The device supports Zonal architecture, located at the edge of the car and connected to the main hub which has a larger bandwidth. It therefore uses the new 10BASE-T1S ethernet protocol (IEEE 802.3cg). This presentation elaborates on the entire trajectory from specification to implementation, using the Tessent Hybrid TK/LBIST flow and Tessent Mission Mode Controller with an APB Interface. The DFT Architecture will be discussed as well as the implications of introducing Siemens IJTAG infrastructure in an existing design, the chosen clocking strategy, scan chain architecture and production test (ATPG) using two test compression blocks (EDTs) instead of one. Decisions are based on doing flat ATPG and keeping the production test flow and coverage as much as possible aligned with the existing standard DFT flow used inside NXP. The end result, a TK/LBIST based extension on top of the standard NXP DFT architecture, ensures a re-usable, scalable and documented DFT architecture for the next generation of Automotive Ethernet Switch devices. Bio: Arjen Bakker works as a Senior Design for Test (DfT) engineer for NXP Semiconductors in Eindhoven, the Netherlands. He has done a bachelor education in Electronic Engineering and he has 25+ years of experience in the field of chip design and test. In 2011 he moved from internal EDA Software Engineering to Digital Design Engineering. Today he is DfT team lead for SoC development in the application area of Automotive and Personal Health. He is a member of NXP’s world-wide DfT-for-Excellence team. ______________________________________________________________________ ABOUT TESSENT SILICON LIFEYCYCLE SOLUTIONS Tessent Silicon Lifecycle Solutions (formerly Mentor Graphics/UltraSoc) is a division of Siemens EDA (Siemens Digital Industries Software). Tessent are widely recognized as the industry market leader in delivering design augmentation and linked applications that detect, mitigate and eliminate risks throughout the IC lifecycle. Tessent solutions help customers address their debug, test, yield, safety, security and optimization requirements for today’s most complex SoCs. Tessent solutions fall into 2 key categories, Tessent Test and Tessent Embedded Analytics. TESSENT TEST | Design for Test (DFT) and Yield Learning DFT and yield learning products for logic, memory and mixed-signal devices. The Tessent Test product suite provides comprehensive silicon test and yield learning applications that addresses the challenges of manufacturing test, debug, and yield ramp. TESSENT EMBEDDED ANALYTICS | SoC Debug and Analytics Tessent Embedded Analytics provides solutions for real-time debug and post-deployment analytics for RISC-V-based and other complex SoCs. _____________________________________________________________________ LEARN MORE Visit the Tessent website: www. https://eda.sw.siemens.com/en-US/ic/t... Email: [email protected] #Tessent #DFTmarketleader